Among the first Gb/s signaling rate I/Os John Poulton and Bill Dally's 4Gb/s FastLink with pre-emphasis equalization, published in 1996 Hot Interconnect Ken Yang's 2.5Gb/s oversampling transceiver, published in 1996 ISSCC
	Clock recovery Stefanos Sidiropoulos' dual-loop DLL, published in 1997 ISSCC
	Ultra-high-speed in CMOS Ramin Farjad-Rad's 8Gb/s 4PAM transceiver, published in 1999 VLSI Symposium Bill Ellersick's 12Gsamples/s ADC for use in PAM encoded links, published in 1999 VLSI Symposium
	Power & cost efficient designs Ken Chang's assymetric serial link used in the Tiny Tera project, published in 1999 VLSI Symposium Edward Lee's low power I/O, to be published in 2000 ISSCC Gu-Yeon Wei's low power I/O, to be published in 2000 ISSCC
	Skew compensation for low-cost parallel links Evelina Yeung's parallel link, to be published in 2000 ISSCC